Complimentary metal-oxide semiconductor (CMOS) transistors formed in silicon have been a dominant technology for modem electronics since they have a very low power consumption and may be easily manufactured. However, the speed of silicon CMOS is limited so that high speed electronic applications are currently being served by the niche technologies silicon emitter-coupled logic (Si ECL) and n-channel GaAs. Both of these niche technologies are high speed, high power consumption technologies, that are costly relative to silicon CMOS; and they provide a level of integration reminiscent of the silicon technology of the early 1980's. There is no current IC production technology that offers at the same time high-speed performance, high levels of integration, and low power consumption.
A compound semiconductor analog of CMOS technology such as a complimentary GaAs FET technology has the potential to achieve high-speed performance with a low power consumption. However, the attainment of a viable GaAs FET technology has been slow in coming due to the very large difference in electron and hole mobilities in III-V compound semiconductors. The electron mobility in an n-channel GaAs FET, for example, is approximately six times higher than that of a silicon CMOS transistor; but the hole mobility in a p-channel GaAs FET is only about the same as that for silicon. Since the performance of a complimentary IC is related to an average of the electron and hole transport properties, GaAs and other III-V complimentary ICs have a potential advantage over silicon CMOS ICs; but this advantage can be improved significantly by the development of a high-mobility p-channel FET.
A viable complimentary III-V IC technology is needed to allow the fabrication of n- and p-channel FETs on a single substrate in a straightforward manner. Such a complimentary III-V IC technology will result in an extremely low static power consumption; and it will allow the use of many circuit design tricks developed for silicon CMOS ICs that minimize the number of transistors required to obtain a given level of functionality. The realization of a high level of integration with a compound semiconductor IC technology can only be realized if the transistor gate and subthreshold currents are reduced to a sufficiently low level.
In the prior art development of conventional (i.e. bulk) complimentary GaAs transistors such as junction FETs (JFETs), most of the speed advantage over silicon is lost since the mobility of holes in bulk GaAs is no better than that in silicon. This low value of the hole mobility (about 200 cm.sup.2 /V-s at room temperature) results in a low p-channel transconductance, g.sub.m, of about 5 mS/mm, and therefore a low switching speed. This p-channel transconductance is about an order of magnitude lower than that of the prior art complimentary conventional n-channel JFET devices, indicating the need for a substantial improvement in the JFET technology before it is viable for wide spread IC use.
In the prior art conventional GaAs metal-semiconductor FET (MESFET), the p-channel transconductance is limited by the bulk hole mobility, as in the case of a conventional p-channel JFET. For MESFETs, the p-channel drive current is therefore about twenty times less and the gate turn-on voltage is lower than for a complimentary n-channel GaAs MESFET. Published research approaches to solving these and other problems with prior art GaAs MESFETs have addressed isolated individual aspects of the problem with no overall approach to device optimization to meet the requirements for complimentary logic circuits. At least three separate areas of concern exist in the prior art GaAs MESFET technology: a satisfactory performance of the p-channel MESFET has not been maintained with a low gate leakage current, with a low subthreshold current, and with compatible processing of an n-channel transistor having the desired characteristics.
The achievement of enhanced transconductance in p-channel AlGaAs/GaAs modulation-doped FETs (MODFETs) and the demonstration of high-speed switching in p-channel MODFET ring oscillator circuits has focused attention on various complimentary heterostructure FET (C-HFET) approaches. A common feature of the various prior art C-HFET approaches is that they make use of the enhanced mobility for holes confined in an undoped region at the interface of an AlGaAs/GaAs heterostructure to achieve improved performance, particularly at low temperatures (77 K.). C-HFETs are the subject of an article entitled "The Potential of Complimentary Heterostructure FET ICs" by R. A. Kiehl, M. A. Scontras, D. J. Widiger, and W. M. Kwapien in IEEE Transactions on Electron Devices, volume ED-34, pages 2412-242, December 1987. A more recent discussion of the various approaches for III-V high speed ICs may be found in a book entitled "High-Speed Digital IC Technologies" edited by M. Rocchi, chapter 5, pages 181-264, published by Artech House, 1990.
C-HFETs are Schottky-gate FETs in which the conducting path is a two-dimensional hole (or electron) gas at the heterointerface between a highly doped wide-bandgap material (AlGaAs) and an undoped smaller-bandgap material (GaAs). The prior art p-channel HFETs show improved performance, particularly at low temperatures (77 K.); but the room-temperature (i.e. 300 K.) performance has been disappointing. The greatest limitation of present C-HFETs is excessively high leakage current at room temperature. A high leakage current increases the static power dissipation and reduces the number of devices that can be incorporated into an IC. The progress in the development of C-HFETs to date has been slow; and these devices have yet to meet acceptable design constraints with regard to threshold voltages and gate leakage currents.
A novel form of C-HFET termed a semiconductor-insulator-semiconductor FET (SISFET) or a heterostructure insulated gate FET (HIGFET) is potentially less sensitive to process variations than conventional C-HFETs because the transistor threshold is largely independent of the distance between the electrons and the gate. Reasonable progress has been made in the development of complimentary HIGFETs (C-HIGFETs) with high performance. C-HIGFET technology offers high performance p- and n-channel devices that use the same InGaAs channel for device design and fabrication simplicity. The use of a common epitaxy for both the p- and n-channel devices, however, results in trade-offs and conflicting design and processing requirements.
Common limitations of the insulated-gate approaches, also termed metal insulator semiconductor (MIS) devices, include higher transistor threshold voltages and an inability to independently adjust the threshold voltage of both n- and p-channel transistors. The resultant IC operation at higher voltages results in inherently higher dynamic power consumption than the C-JHFET approach of the present invention, because the dynamic power dissipation increases as the square of the power supply voltage.
The present invention uses a complimentary JFET technology that uses a different epitaxial layer structure in the p- and n-channel transistors, thereby allowing each device to be independently optimized for high performance and ease of manufacture.
Many different types of complimentary FETs in silicon and GaAs have been patented, and these patents are summarized below:
U.S. Pat. No. 4,811,075 discloses a high voltage metal-oxide semiconductor field-effect transistor (MOSFET) in silicon that can be made either as a discrete or as an integrated device having either n-channel or p-channel conductivity. These high voltage (up to 300 volts capability) transistors are formed by connecting an insulated gate field-effect transistor (FET) and a double-sided junction gate field-effect transistor (JFET) in series. Devices of opposite conductivity may be combined in a complimentary manner on the same chip. MOSFET devices cannot be formed in GaAs and other compound semiconductors since native oxides do not exist for these materials as in silicon.
U.S. Pat. No. 5,122,851 discloses a trench gate JFET transistor in silicon suitable for use in interfacing large numbers of photodetectors with associated circuitry as in an infrared array image detector. The gate in this invention is recessed in a trench formed in the substrate between a drain and source region. The trench is preferably of sufficiently depth to mitigate the generation of 1/f noise in the transistor. Devices of opposite conductivities may be combined in a complimentary manner on the same substrate. U.S. Pat. No. 5,010,025 discloses a method for forming the above trench-gate JFET device. The gates of the present invention are not recessed in a trench as in the above patents (although the entire n-channel transistor of the present invention is formed in a trench for reasons of ease of manufacture rather than to reduce 1/f noise).
U.S. Pat. No. 4,117,587 discloses a negative resistance semiconductor device formed by interconnecting in series two complimentary JFETs with the gate of each device connected to the drain of the other device of the opposite conductivity type. The result is a two-terminal circuit device that exhibits a current-versus-voltage characteristic having a negative resistance region. The present invention comprises more than two terminals and does not show a negative resistance characteristic.
U.S. Pat. No. 5,130,770 discloses a JFET formed by a silicon-on-insulator technology. The drain and source of the JFET are formed on a semiconducting island supported by an electrically insulating layer that is preferably SiO.sub.2. Semiconductor oxides are not used in the formation of compound semiconductor devices as in the present invention.
U.S. Pat. No. 5,031,007 discloses complimentary FETs formed from a compound semiconductor strained-layer superlattice comprising a plurality of alternating layers of two different semiconductor materials, one forming quantum-well layers and the other forming barrier layers. The strained layer superlattice increases the hole mobility by splitting the degeneracy of the valence band over that of the material in bulk form. The p-channel transistor in the present invention uses at least one strained quantum-well layer to increase the hole mobility by splitting the valence band degeneracy; and no strained layers or quantum wells are present in the complimentary n-channel transistor in the present invention.
U.S. Pat. No. 5,142,349 discloses a C-HFET device that attempts to solve a problem with conventional HFETs due to a mismatch in the p- and n-channel threshold voltage and operating characteristics. This invention uses multiple electrically isolated vertically aligned channels to form a plurality of vertically stacked FETs with the channel regions controlled by a single gate electrode. In the preferred embodiments of this invention, aluminum antimonide (A1Sb) and gallium antimonide (GaSb) am preferably used for the p-channel devices and indium arsenide (InAs) and AlSb or the complimentary n-channel devices.
U.S. Pat. No. 5,243,206 discloses a heterostructure field-effect transistor structure having vertically stacked complimentary n- and p-channel devices. The n- and p-channel transistors share a common gate electrode with the n and p channels positioned parallel to each other and vertically spaced by a predetermined separator thickness. Although this vertically stacked design is intended to dramatically reduce the chip size of compound semiconductors and increase the device packing density, it does so at the expense of a more complicated epitaxy and an increased manufacturing difficulty. The n- and p-channel transistors are not capable of independent operation due to the common gate electrode. A positive voltage on the gate turns the n-channel transistor on while simultaneously turning the p-channel off. This mode of operation may be advantageous for certain applications; but it is more restrictive than one in which the n- and p-channel transistors are completely independent as in the present invention.
U.S. Pat. No. 5,060,031 discloses a complimentary heterojunction field-effect transistor with an anisotype n.sup.+ gate for p-channel devices. The heavily n-doped anisotype layer underneath the gate electrode forms a semiconductor junction that replaces or augments a Schottky-barrier junction for the purpose of increasing the p-channel turn-on voltage to nearly 1.7 volts. In this prior art complimentary HFET, a common channel (preferably InGaAs) is used for both n-channel and p-channel transistors. The use of a common epitaxy for both n- and p-channel transistors results in some layers that are common to both transistors, and limits the ability to independently optimize each transistor's characteristics.
A primary concern in the design of compound semiconductor complimentary field-effect transistors is the structure of the channel region underneath the gate electrode since the channel region performance largely determines the overall performance of the transistor. This is especially true of p-channel transistors.
An advantage of the complimentary junction heterostructure field-effect transistor (C-JHFET) of the present invention is that bandgap engineering by means of heteroepitaxy may be used to optimize the performance and speed of the p-channel device, and to dramatically increase it over prior art p-channel MESFET and HFET devices.
Another advantage of the C-JHFET of the present invention is that once the design of the p-channel device is optimized, a complimentary n-channel device may be formed in a compatible manner.
These and other advantages of the C-JHFET will become evident to those skilled in the art.